This application is based on, and claims priority to, Japanese Application No. 2002-105898, filed Apr. 9, 2002, in Japan, and which is incorporated herein by reference.
(1) Field of the Invention
This invention relates to a semiconductor memory and, more particularly, to a semiconductor memory, such as a content addressable memory (CAM), which outputs an address where data to be retrieved is stored.
(2) Description of the Related Art
Retrieval operation for retrieving an address where input data (data to be retrieved) is stored is the characteristic operation of CAMs. Data to be retrieved input from the outside and data in a cell are compared by this retrieval operation. Cells in a CAM which enable this operation have a structure shown in FIG. 19.
As shown in FIG. 19, one cell included in a CAM includes metal oxide semiconductor (MOS) transistors (hereinafter referred to simply as transistors) 1a, 2a, 3a, 6a, 1b, 2b, 5b, and 6b and inverters 3a, 4a, 3b, and 4b. 
The transistors 1a and 2a and the inverters 3a and 4a store an ordinary bit. The transistors 1b and 2b and the inverters 3b and 4b store an auxiliary bit.
The transistors 5a, 5b, 6a, and 6b judge whether or not signals applied to retrieval data lines SD and XSD match data which has been stored in the cell.
Signal lines XBL0, BL0, XBL1, and BL1 are used to write and read data.
Data to be retrieved is input to the retrieval data lines SD and XSD. A word line WL is a selection control signal line located in the direction of a row of cells. A match line ML is a match detection signal line for transmitting the result of matching located in the direction of a row of cells.
Now, operation in the above conventional CAM will be described. FIG. 20 is a truth table showing the state of the cell shown in FIG. 19. As shown in FIG. 20, the cell shown in FIG. 19 stores the logical value xe2x80x9c1,xe2x80x9d xe2x80x9c0,xe2x80x9d or xe2x80x9cX (undefined).xe2x80x9d To be concrete, assuming that the input sides of the transistors 6a and 6b are N1 and N2 respectively, the state in which N1 is xe2x80x9cLxe2x80x9d and N2 is xe2x80x9cHxe2x80x9d corresponds to xe2x80x9c1,xe2x80x9d the state in which N1 is xe2x80x9cHxe2x80x9d and N2 is xe2x80x9cLxe2x80x9d corresponds to xe2x80x9c0,xe2x80x9d and the state in which N1 is xe2x80x9cLxe2x80x9d and N2 is xe2x80x9cLxe2x80x9d corresponds to xe2x80x9cX.xe2x80x9d
For example, if the logical value xe2x80x9c1xe2x80x9d has been stored and xe2x80x9c0xe2x80x9d is input as a value to be retrieved, that is to say, if the retrieval data line SD is put into the xe2x80x9cHxe2x80x9d state and the retrieval data line XSD is put into the xe2x80x9cLxe2x80x9d state, then the transistors 5a and 6a go into the ON state and the transistors 5b and 6b go into the OFF state. As a result, the match line ML is grounded by the transistors 5a and 6a and goes into the xe2x80x9cLxe2x80x9d state. A mismatch therefore will be detected.
On the other hand, if the logical value xe2x80x9c1xe2x80x9d has been stored and xe2x80x9c1xe2x80x9d is input as a value to be retrieved, that is to say, if the retrieval data line SD is put into the xe2x80x9cLxe2x80x9d state and the retrieval data line XSD is put into the xe2x80x9cHxe2x80x9d state, then the transistors 5b and 6a go into the ON state and the transistors 5a and 6b go into the OFF state. As a result, the match line ML is not grounded and remains in the xe2x80x9cHxe2x80x9d state. A match therefore will be detected.
The above is basic operation in one memory cell.
Now, a content addressable memory word (hereinafter referred to simply as a memory word) in which a plurality of memory cells, each of which is the same as the one shown in FIG. 19, are connected will be described.
FIG. 21 is a view showing the structure of a memory word. As shown in FIG. 21, a memory word includes a plurality of memory cells connected, each of which is the same as the one shown in FIG. 19. In this example, only two memory cells 10 and 11 are shown, but in reality more memory cells are connected.
The memory cells 10 and 11 are wired-OR-connected to a match line ML. If data to be retrieved input to the memory cells 10 and 11 via retrieval data lines SD1 and XSD1 and retrieval data lines SD2 and XSD2, respectively, does not match data which has been stored in them, then the match line ML is grounded.
The memory cell 10 includes storage sections 10a and 10b and transistors 10c through 10f. Each of the storage sections 10a and 10b corresponds to the two transistors and two inverters shown in FIG. 19.
The memory cell 11 also includes storage sections 11a and 11b and transistors 11c through 11f. Each of the storage sections 11a and 11b also corresponds to the two transistors and two inverters shown in FIG. 19.
An inverter 13 inverts a signal applied to the match line ML and outputs it as an output signal OUT.
When a pre-charge line MLEZ goes into the xe2x80x9cLxe2x80x9d state, a transistor 12 pre-charges the match line ML.
Now, operation in the above example will be described.
FIG. 22 is a timing chart for describing operation in the above example.
At time T0 the circuit is in a standby state. The pre-charge line MLEZ is in the xe2x80x9cLxe2x80x9d state (see FIG. 22(A)), so the match line ML is in a pre-charged state.
At time T1 the pre-charge line MLEZ goes into the xe2x80x9cHxe2x80x9d state (see FIG. 22(A)). Then the transistor 12 goes into the OFF state and the match line ML is released from the pre-charged state.
At time T2 the data xe2x80x9c0xe2x80x9d to be retrieved is input. Then the retrieval data line SD1 goes into the xe2x80x9cHxe2x80x9d state (see FIG. 22(B)) and the retrieval data line XSD1 goes into the xe2x80x9cLxe2x80x9d state (see FIG. 22(C)).
Assuming that the data xe2x80x9c1xe2x80x9d has been stored in the memory cell 10 at this time, output from the storage section 10a goes into the xe2x80x9cHxe2x80x9d state and output from the storage section 10b goes into the xe2x80x9cLxe2x80x9d state.
As a result, both the transistors 10c and 10d go into the ON state. Therefore, the match line ML is grounded and goes into the xe2x80x9cLxe2x80x9d state (see FIG. 22(D)).
The match line ML goes into the xe2x80x9cLxe2x80x9d state and at time T3 output from the inverter 13 goes into the xe2x80x9cHxe2x80x9d state. This indicates that a mismatch has occurred in the memory word.
At time T4 the pre-charge line MLEZ goes into the xe2x80x9cLxe2x80x9d state and the match line ML is charged and goes into the xe2x80x9cHxe2x80x9d state. As a result, one cycle ends.
By the way, the above retrieval operation is performed on the entire chip. For example, if a memory word includes N cells and there are M memory words in the entire device, then Nxc3x97M memory cells will operate at the same time.
Operating a memory cell involves charging and discharging the match line ML and driving the retrieval data line SD. Therefore, a large amount of power will be consumed to drive these Nxc3x97M memory cells.
The present invention was made under the background circumstances as described above. An object of the present invention is to provide a semiconductor memory which consumes only a small amount of power at retrieval operation time.
In order to achieve the above object, a semiconductor memory comprising a plurality of content addressable memory words, a plurality of memory cells connected to each content addressable memory word, memory word blocks each including N content addressable memory words, a storage circuit which has stored a plurality of patterns of information indicative of whether to activate each memory word block, an activation circuit for activating each content addressable memory word block according to a specified pattern in the case of specification information for specifying a predetermined pattern from among the plurality of patterns of information which has been stored in the storage circuit being input, and a specification circuit for specifying a content addressable memory word which has stored data corresponding to data to be retrieved from among a group of content addressable memory words activated by the activation circuit in the case of the data to be retrieved being input is provided.
The above and other objects, features and advantages of the present invention will become apparent from the following description when taken in conjunction with the accompanying drawings which illustrate preferred embodiments of the present invention by way of example.